I will be releasing a new v5 firmware in the next week or so if anyone is interested in testing. I just need to do a bit more testing here first.

Some up the updates include:

The Wiznet driver has been updated and I now have driver versions for the newer Wiznet W5500-based Ethernet modules as well as the currently shipping W5200-based WIZ820IO module.

This does mean that when doing future firmware updates, you must select the firmware file that matches your hardware. To make this more manageable the Ethernet module type will now be part of the firmware file name like the controller name is now, such as E682v5.050-W5200.eeprom.


Minor web page layout changes such as inclusion of Wiznet type and Wiznet driver version number in firmware version display.

Firmware update via LAN now has a longer timeout delay.

Packet processing logic has been optimized. Previously the entire incoming packet was read into a packet receive buffer. Then the header was analyzed to determine if it was a valid packet and if so, the DMX bytes were copied from the packet buffer to the DMX buffer. The new logic reads only the header into the packet buffer. If the packet is rejected the data bytes are discarded. If the packet is accepted the data bytes are read directly from the Wiznet to the DMX buffer. This change, while not visible to the end user, should allow for some increase in the number of supported universes, and was also needed for support of SACN priority.

SACN priority is now supported. If multiple senders are sending packets to the same universe at different priorities, only the packets from the highest priority sender will be accepted. A priority value is maintained for each universe and resets to 0 if the high-priority sender stops sending for 2 seconds.

New power on self tests can detect certain hardware failures and indicate the fault using the on-board LEDs. Currently supports detection of failures in the crystal oscillator and Wiznet module. This is to assist troubleshooting in situations where there is not enough functionality to display the web page.

Added support for DDP pixel protocol.

Fixed bug re init of NULLS config data.

Added support for pixel type RELAY. Pixel type RELAY can operate 1 low-current relay per output on an E682 and 2 low-current relays per output on an E6804. A non-zero value on channel 1 turns on the relay on the DATA output and a non-zero value on the 2nd channel turns on the relay on the CLOCK output (E6804 only).

Added support for MY9231 pixels.

Zigzag: On version 4 firmware, the zigzag function assumed that the pixel strings would be an even multiple of the length of the matrix columns. In practice this is not always the case. Version 5 was intended to address this. However, when string length is not an even multiple of column height it can get very messy since a single pixel string can have multiple non-contiguous blocks of pixel addresses. I have decided to go back to the original scheme that only supports 'standard' dimension matrices and non-standard matrices will need to have pixel address assignments handled at the sequencing software level.