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Thread: First PCB design - request for comments

  1. #11
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    Default Re: First PCB design - request for comments

    Great feedback, thank you all. Let's see if I can hit all of the questions first:

    @smartalec: Yes, this is an LED controller driven directly by ethernet and driving 64 channels.

    @budude: I was going to compare/contrast this to DynamoBen's PropController, or maybe jstjohnz' E680/681, but it is optimized for one purpose and therefore much more application specific.
    * DesignSpark does have DRC capability and I did run it. There were no spacing violations, but many "pad to silkscreen", "via to silkscreen", "track to drill hole" and "annular ring too small" (on the RJ45 jacks only) errors. I haven't fixed them yet because I don't know that the design rules I used are correct in the first place. I'm using the DesignSpark default technology file and rules that came with the tool. I have to figure out where to get real, official DesignSpark technology files for SeeedStudio. While I can't imagine having to code that up myself, I felt the same about component libraries until I gave in and created all my own components. So while there were no DRC track spacing violations, given the feedback that may be due to incorrect rules in the technology file I used (default).
    * Good comments on the common ground. Each RJ45 does drive 8 individual channels. The GND on this controller board also needs to be brought to the distribution boards for each channel. Generally this will be "for free" because they will share a common power supply (+5V and GND). However, I did provide for the case where the controller board is powered by a separate supply; that's why there's a third terminal on the power connector (upper left corner) to provide for a GND wire out. I would have prefered a 9P9C RJ45a jack but my searches for that failed...

    @LabRat: You nailed it. In my original post I stated that I was amazed at how long this takes to do (well). I already have 10x more hours into this than I anticipated. What you see here is the result of the many hours it has taken me to go from all components placed in a heap off the board to now with the components all meticulously, manually placed, attempting to minimize trace length, congestion, crossings, etc. These actual traces are the work of the autorouter. I've seen areas where "I could have done that better by hand" but I haven't until I get some feedback that I'm at least close with the big picture (overall design, component selection and placement).

    @ebrady: Aside from preference, are there pros/cons to the oval vs. round IC pads? I "borrowed" them from an existing library and have no idea if they are correct. Maybe I should use round because they are simpler to define correctly?
    * The DRC called out "annular ring too small - size is 4, should be 5" on the mounting holes for the RJ45 jacks. I started with a component I found in an AMP connector library. This is just a common 556416-1 jack. The hole looks like it's defined as a pad, width is 0.136" and hole size is 0.128". I measured the tabs on the jack I have with a caliper and read about 0.12". I guess the complaint is that the copper around the hole is too thin after the hole is drilled (136-128=8; 8/2=4; 4 is width of the ring?) Is the copper ring needed at all? This isn't a pad, just a mounting hole. Does the copper ring provide some structural stability to the board where the hole is, or make it easier to insert/remove the jack mounting posts?
    * I absolutely do intend on a copper pour on the bottom layer, for GND. My protoype design is working, but I have SI issues that are causing glitches. No wonder, with all the wires running around in space and the long lengths and no decoupling caps. I've been obsessing with the decap placement (based on advice from others) and as you see the only way I could have gotten closer to the PWR/GND pins would be to open the IC package. I hope that a GND plane will help me here also.

    So the outstanding issues (aside from manually routing, or at least fixing, the traces) are:

    1) How/where can I get a technology defintion file, with accurate design rules, for DesignSpark & SeeedStudio? I'll be searching after I hit "submit" on this post.
    2) What is the "correct" hole size to accommodate through hole pins that are not actually round, or even those that are? For instance, I'm using a Tyco/TE 1-390261-4 (datasheet here: http://www.te.com/catalog/pn/en/1-390261-4) I read it as saying that the pins are 0.024" x ??", and use a 0.039" hole. What drill size is that (if that is correct in the first place)? What size pad do I need to define for this?

    Thanks for all the responses. I'll get there, although it may take me a few more passes.

  2. #12
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    Default Re: First PCB design - request for comments

    Still toiling away...

    @n1st: Thanks for the great suggestions.
    * You clearly took more than a casual look at the design (schematic and board). Did you mean to say you use square pads for anodes (instead of cathode)?
    * The strange stuff going on in the schematic at the Wiznet ulhs was due to a drag/move. The logical connectivity was correct, it was just drawn with overlapping lines.
    * Very good suggestion about pulling RESn high, but from the Propeller documentation, when BOEn is tied low, RESn becomes a weak output (tied to VDD through 5k) to monitor the Prop reset condition, but also allowing it to be pulled low to cause a reset. What I've attempted to implement is a momentary pushbutton that will bring RESn low, and that should then stay low (also resetting the WIZnet module) until the Prop comes out of reset. That's the theory, anyway.
    * Yes, I was trying to use PWR/GND symbols to tie nets together logically without actually drawing the wiring on the schematic. I guess I didn't make the best choices of where/when, though.
    * I didn't correctly assign all the PWR/GND nets to the correct (not signal) category. Fixed that now.
    * I've changed packages to use all round pads. I'll see how that works. That should also make acute angles impossible, I think.
    * Added clarification to the CONN outline. Still working on how I get (automatic) net name on the silkscreen. I can do it on schematic symbols, but PCB packages seem not to work the same way.
    * Any suggestions on mounting hole size? Should they also be plated at the edges?

    Regarding design rules: First, I can't find any SeeedStudio rules for DesignSpark. I found Eagle rules but no way to translate them (there is a way to translate libraries, though).

    Second, I must be missing something (misunderstanding or bad math/measurement/precision on my part). If 10/10 rules are not agressive, and I have all through hole 0.1" pitch parts, then why is routing between pins not good. The pads are 60 mils wide, that leaves 40 mils spacing, and if I use 10 mil traces that leaves 10 mil spacing plus another 10 mil "slack". Other than wider PWR/GND traces, that seems to be OK, yet there have been comments about traces being too close. What am I missing?

    Now I'm setting out to be an artist. Manual routing. The whole thing. Yikes...

    Thanks.

  3. #13
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    Default Re: First PCB design - request for comments

    I'm not overly familiar with the prop, so my comment about the reset pullup doesn't apply here; many other processors do require or recommend one.

    For diodes, the square pad is usually the cathode. Maybe because it is usually the banded or marked leg? That holds true for tantalums as well (they tend to mark the positive) but not alumonum lytics which tend to mark the negative. I guess it is more out of habit. I did get burned once by an LED that had both a pin 1 mark and a cathode mark; manufacturing guessed wrong and I had to turn them around on a dozen prototypes :-)

    Round pads should avoid acute angles as long as the trace is running to the center of the pad. Some tools let you hit the pads off center. Look at the trace from pin 5 of the '595 to the RJ45 - they look to be hitting the connector pad off center.

    I usually don't automatically put net names on the silk; it is often easier to add the annotations as text on the silk by hand.

    For mounting holes, I usually use 0.127" It's a standard size and fits a 4-40 screw. I don't think Seeed or Itead do non-plated holes so you will want a bit of annular ring to pass DRC. Otherwise, you can always tie the mounting holes to the ground plane.

    Traces between DIP pads are fine if you are using a board with solder mask. Without mask, it is easy to short the trace to the pad when soldering. Places on your board that look a bit close are the top (traces from ic9p11 and ic9p15), IC4p4, and IC2p3 where it loops by IC1p5

    /mike

  4. #14
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    Default Re: First PCB design - request for comments

    Quote Originally Posted by n1ist View Post
    For mounting holes, I usually use 0.127" It's a standard size and fits a 4-40 screw.
    That's good to know.

    Quote Originally Posted by n1ist View Post
    I don't think Seeed or Itead do non-plated holes ...
    Yep, all my holes from Seeed came plated.

    \dmc
    ________________________
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    or a hardware engineer with a compiler is a liberal-arts major with either.
    Christmas lights: http://www.PacificaLights.info/
    uC/LED hacking: http://www.dmcole.net/

  5. #15
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    Default Re: First PCB design - request for comments

    I hate to seem like a broken record, but it seems so wrong to not have a common return in every output cable. The return path for the current becomes quite complex, and from an emi pov would be a big problem in any commercial product that needs to conform to FCC emissions rules.

    Depending on the details of the load on the output connectors, you might want to add series current limit resistors between the '595 chips and the RJ45 connectors. Also, be aware that the output current drive of most (if not all) '595 chips is limited, so they cannot directly drive 8 LEDs at full power (25 mA each). So do you have some sort of external driver chips (like ULN2803)?

    I think that it would be a good idea to move as many of the traces to one side of the board as possible, so that the ground fill is as clean as possible with as few holes or slots as possible, and with any slots in the ground plane as short as possible.

    The single most critical signal on your board is the serial clock signal going to pin 11 of the '595 chips. It's hard for me tell what your intent is, since IC4 and IC5 do not appear to have that signal wired up. Do you have four such clock signals, or only one? In any case, I suggest that you pay a lot of attention to keeping those signals short and direct, without any branches (if possible), and that you try to place a return (ground) path on the opposite side of the board, directly under that (those) traces.
    Phil

  6. #16
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    Default Re: First PCB design - request for comments

    As Phil mentioned, there are some traces that you may want to run very cleanly and as short as possible. I would hand run those and then lock them (I'm assuming your board editor as that feature) and then try your auto-router. You also indicated you were going to add a ground plane/pour. You may want to do that now since the extra traces created by all the ground runs will overly complicate the routing paths. I also agree that you may want to rethink about have the common return/source within the cable group instead of hoping you get it from somewhere else.
    Brian

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  7. #17
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    Default Re: First PCB design - request for comments

    I'm just now finishing up for the day. Wow, what a day it was. Big difference between the initial auto-routed version and this one, which is 100% OCD-manual routed. I believe I've taken into account all of the input from this post, with the exception of running ground along with the signals going out the RJ45 jacks. The reason is that they are signals only, not driving the LEDs. There is little current (the Propeller drove them fine at 3.3v, the '595s should be even better at 5v). Also, each bundle of 8 channels is going to another board (yet to be completed) that will have a #10AWG ground wire in common with the ground on this controller board. There should be little current and IR drop. I've done some testing, but of course things might be different when I fire it up.

    I've still not been able to find any technology file for SeeedStudio and DesignSpark (just Eagle). If anyone has an idea on that I'd appreciate it.

    I have a problem with every power trace (50 mil). Every time I connect power to a pad I get this DRC error: "Track to Drill Hole error (T-D) at (9200 5450) on layer "Top Copper. Track too wide to backoff from drill."

    I understand the words, but how can I fix this? Do I need bigger pads for the wider power traces? That will be a big problem.

    What I'm posting is both layers, without the copper pour for GND. I've been able to avoid most routes on the bottom copper. I'm wondering if it's worth it to use a via on the one signal per RJ45 jack that is on bottom copper. I don't konw if it's better to avoid the resistance of a via on a signal wire (only 200kHz signal) or reduce the slots in the GND plane even more. Thoughts?

    Oh, and I also am unsure about the relative placement of the 5MHz crystal and the decoupling capacitor on the top-middle of the Propeller chip. I opted to put the cap closest, then the crystal. This is based on recommendations to keep the cap as close as possible and with short PWR/GND leads. Does this seem like a good choice, or should the crystal really be closest?

    Finally, I had a problem where I tried to use a via as dual-purpose: to transition from top to bottom copper on a power trace and to connect a lead of a capacitor. The DRC complained. Is this a valid complaint or can it be ignored? You can see that I had to stagger the capacitor away from the via - C4, at the upper right-hand corner of MODULE1.

    Thanks again for all the help. This has been a long, but fun day. Now I just need a logo...

    NetworkedLights2v2 (PCB).pdf

  8. #18
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    Default Re: First PCB design - request for comments

    Heres some good DRC rules that will see you fine.. However, just because you can make a track 7mil, don't do make it 7mil unless you have to.. i

    1 & 2 layer Process 1 oz / 35um 2 oz / 70um 3 oz / 105um
    Minimum trace width 7 mils 8 mils 10 mils
    Minimum clearance 7 mils 8 mils 10 mils
    Minimum via/hole size (specified) 12 mils 12 mils 12 mils
    Minimum pad for plated hole/vias 26 mil 30 mils 34 mils
    Minimum plated slot 32 mil 30 mils 28 mils
    Minimum Soldermask Clearance 4 mil 4 mil 4 mil
    Minimum Silkscreen Clearance 4 mil 4 mil 4 mil
    Minimum Silkscreen line width 6 mils 6 mils 6 mils
    Minimum board copper/edge margin 10 mils 10 mils 10 mils

  9. #19
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    Default Re: First PCB design - request for comments

    Thanks for the values, MPH. I still need to get past the 50mil trace/drill hole error being reported. I do see that if I use a square pad the problem disappears, but then I'll have square pads that are not PIN1. That doesn't sound too good.

    I'm still tweaking (hopefully almost done) and wonder if it is best practice to "double-strap" GND lines? Here's what I mean: I've not used any traces for connections to GND, expecting bottom copper to provide a GND plane. That poses a problem because until I have a (bottom) copper pour, I have opens. When I pour copper, there's no way to see anything else on the board (I haven't found a way to re-order layer drawing, although I can turn layers off). So I though, how about running a separate GND strap and wiring everything together, without (or eventually, in addition to) the GND plane. So I started off running a second power (GND) trace on top copper. Then it occurred to me that this "belt-and-suspenders" approach might lead to problems in the form of ground loops.

    So, do I just leave the layout as-is and rely on the GND plane to complete the opens, do I run a GND trace on top copper, or do I run a GND trace on bottom copper, to ultimately be incorporated into the bottom copper pour?

    Thanks!

  10. #20
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    Default Re: First PCB design - request for comments

    I think part of the issue is that you can't tell what is grounded from the pour. I suggest you change all the ground pads (except maybe for the input) to thermals instead of full connects. This will help you a bunch during soldering as you won't have to heat up lots of copper to solder - also - you'll be able to see them in your editor.

    This last version is a staggering improvement btw! It still looks like a few traces run pretty close here and there but then again, that may just be the PDF conversion as well. You might try generating the Gerbers and then using gerbv (or similar) to view it for real. You will want a Gerber viewer at some point to double check all your layers including the silks anyway.
    Brian

    Christmas in San Jose! - WEB - FB - VIDEOS
    Halloween in San Jose! - FB
    2014 Halloween Show - Homemade tombstones, Video Projection - not much new this year...
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    Ignorance is Temporary - Stupidity is Forever...

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